Senior Design Engineer Jobs Vacancy in Xilinx Hyderabad
Xilinx Hyderabad urgently required following position for Senior Design Engineer. Please read this job advertisement carefully before apply. There are some qualifications, experience and skills requirement that the employers require. Does your career history fit these requirements? Ensure you understand the role you are applying for and that it is suited to your skills and qualifications.
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Senior Design Engineer Jobs Vacancy in Xilinx Hyderabad Jobs Details:
Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).
Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!
Design Engineer 2
- Responsible for Physical Design from RTL to GDS2 for blocks at the 7nm technology node.
- Experience in physical design, and IC design flow (RTL to GDSII implementation) including flow steps such as floorplanning, powerplanning, CTS and routing is required.
- Proficient in signoff checks viz. static timing analysis (STA), physical verification, EMIR analysis and timing closure.
- Working experience in PERL and TCL programming.
Master’s/Bachelor’s Degree in Electrical/Electronics Engineering
Years of Experience
3 to 5 years of experience in ASIC Synthesis, PnR flows and design closure.
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